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| jonwil | MohammadAG: ping | 09:54 |
|---|---|---|
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| MohammadAG | Pong | 11:02 |
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| jonwil | MohammadAG, what do I do to get operator-name-cbs-widget into CSSU-T? | 11:26 |
| jonwil | Its in the CSSU repos now | 11:26 |
| jonwil | how do I get it into the next version of CSSU-T? | 11:26 |
| jonwil | guess he left :P | 11:31 |
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| MohammadAG | merlin1991: Tell him he doesn't have to do anything | 11:42 |
| freemangordon | DocScrutinizer ping | 12:00 |
| DocScrutinizer51 | freemangordon: at work | 12:01 |
| DocScrutinizer51 | a minute | 12:02 |
| freemangordon | Both BootROM and x-loader on n900 are thumb compiled. Anywa, ping me when you have time | 12:02 |
| freemangordon | Anyway* | 12:02 |
| DocScrutinizer51 | will do | 12:02 |
| freemangordon | 10x | 12:02 |
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| DocScrutinizer | 10x? | 19:34 |
| MohammadAG | DocScrutinizer: Ten x | 20:09 |
| MohammadAG | Tenx | 20:09 |
| MohammadAG | Tanzania | 20:09 |
| MohammadAG | Tanx | 20:09 |
| MohammadAG | Thanx | 20:09 |
| MohammadAG | Thanks | 20:09 |
| MohammadAG | Get it? | 20:09 |
| MohammadAG | Tanzania was iOS autocorrect | 20:09 |
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| Raimu | DYAC | 20:17 |
| andre__ | YMCA | 20:39 |
| Raimu | ...that's random, but funny. | 20:44 |
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| DocScrutinizer | freemangordon: ping | 22:09 |
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| freemangordon | DocScrutinizer pong | 22:37 |
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| freemangordon | DocScrutinizer, as I already told you today both bootrom and xloader (nolo) are thumb compiled. I've been searching alot these days and AIUI two erratas in question regarding thumb are *NOT* mutually exlusive. Workaround for first (430973) is to flush BTB on every context switch. This is done by using special instruction to system control coprocessor. There is a special bit in one of the | 22:44 |
| freemangordon | control registers which enables those instructions otherwise they are treated as NOPs. (TBC) | 22:44 |
| freemangordon | The second errata has 2 workarounds - either do not enable the bit needed for 430973 errata workaround *OR* make sure that L1 Array debug register is 0 | 22:46 |
| DocScrutinizer | freemangordon: I don't think you can know what bootrom code looks like, afaik it's only documented to what it *does* | 22:46 |
| DocScrutinizer | and xloder != NOLO | 22:46 |
| freemangordon | well, it could be read from linux, if you wish search xda-developers, they have omap3430 disassembled | 22:47 |
| freemangordon | bootrom | 22:47 |
| DocScrutinizer | hmm, ok | 22:48 |
| freemangordon | And I disassembed NOLO here, it is thumb compiled | 22:48 |
| DocScrutinizer | was too bad if they shipped chips with buggy mask programmed firmware ;-P | 22:48 |
| freemangordon | and you were correct, NOLO does not run in secure mode (secure as in TrustZone or whatever it is) | 22:49 |
| DocScrutinizer | anyway, when the ne problem is about flushing pipelibnes/caches on context switch, then xloader and even NOLO are kinda out of the line of fire, as they all ahve no preemptive multitasking | 22:49 |
| freemangordon | Incorrect, Security Manager is in boorom | 22:50 |
| freemangordon | in Ll cache is controlled via calls to it | 22:50 |
| DocScrutinizer | eh? | 22:50 |
| freemangordon | sorry, L2 cache | 22:50 |
| DocScrutinizer | I missw | 22:51 |
| DocScrutinizer | missed the link | 22:51 |
| freemangordon | there are several places in kernel when cache is invalidated, that is achieved via SM call | 22:51 |
| DocScrutinizer | between preemptive multitaksing and bootrom | 22:51 |
| freemangordon | and SM call is handled in bootrom | 22:52 |
| DocScrutinizer | and esp the fact that neither bootrom nor xloader or NOLO do have any (preemptive, or whatever) multitasking | 22:52 |
| freemangordon | the code is called from kernel | 22:52 |
| freemangordon | which is | 22:53 |
| DocScrutinizer | so they can all happily ignore all SiERR related to randomly happening context switches, as they are all strictly monothreaded and in that sense 1-dimensional and deterministic | 22:53 |
| DocScrutinizer | in a strictly sequential code there's no need for flushing any cache or pipe | 22:54 |
| DocScrutinizer | except for branches, and even those are predefined | 22:54 |
| freemangordon | no, the problem is that it could happen to execute thumb instruction in ARM mode and vice-versa | 22:54 |
| DocScrutinizer | yes, exactly | 22:55 |
| DocScrutinizer | as context switches would switch between the two domains and nothing got implemented on hw level to deal with that | 22:55 |
| DocScrutinizer | that's my idea of where problems are from | 22:55 |
| freemangordon | why domains? | 22:55 |
| freemangordon | AIUI we are talking about virtual(or physical) adresses | 22:56 |
| freemangordon | and I think ROM code is copied in RAM | 22:56 |
| freemangordon | anywa, my point was, that we should never hit second errata, as the register in question is neve modified | 22:57 |
| freemangordon | never* | 22:57 |
| freemangordon | bootrom does not touch it, and it is too late after switch to unsecure mode | 22:58 |
| freemangordon | maybe beagleboard, because of some debugging or whatever code in some rom extension modifies it | 22:59 |
| freemangordon | the errara says that L1 AD register is undefined on *RESET*, not a word about power-on | 22:59 |
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| freemangordon | BTW I am not sure if it is not possible to flush BTB by just disabling and re-enabling branch prediction (to wotkaround 430973) | 23:02 |
| DocScrutinizer | you need to find code that reliably triggers the error, then test what can be done to no longer make it happen, and finally do a theoretical proof why the fix is universally valid and not limited to the set of tests you did | 23:04 |
| freemangordon | well, that could be problematic, I really have no idea how to trigger that | 23:05 |
| DocScrutinizer | for your assumed register that never gets touched on N900 the proof seems quite straight and simple, no? | 23:05 |
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| freemangordon | no | 23:05 |
| freemangordon | There is no way to read that register oudside the secure code | 23:06 |
| DocScrutinizer | a) tough the register and cause an exception based on that SiERR, and b) show that actually N900 usually doesn'T use that reg anywhere | 23:06 |
| DocScrutinizer | touch* | 23:06 |
| freemangordon | even reads are disabled | 23:06 |
| freemangordon | if I could write to it then I will write 0 and be sure second errata is 100% workarounded | 23:08 |
| freemangordon | but there is just no way | 23:08 |
| DocScrutinizer | :nod: | 23:08 |
| freemangordon | but I can guess on power-on the content of that register is 0 | 23:09 |
| DocScrutinizer | so there's another way: a) show the datasheet/whatnot factoids that say "write 0 there and the problem is fixed", rgen b) disassemble bootrom, xloader, and NOLO and show one of them is actually writing 0 to that register | 23:10 |
| freemangordon | that is what i have done :D | 23:10 |
| freemangordon | oops | 23:10 |
| freemangordon | sorry, misunderstood you | 23:11 |
| DocScrutinizer | a2) write to TI and ask what's the POR-default of that register, and if that is sufficient for the assumed-to-fix-it 0 that needs to be written there | 23:11 |
| freemangordon | that was my idea, bu NOONE is touching that register | 23:11 |
| Sc0rpius | my phone is still landscape :( | 23:11 |
| DocScrutinizer | freemangordon: SPRUF98D is the code of the OMAP3430 datasheet, check what is written there about that register. Might depend on bootmode set by hw pins at low/high on power-on, and whatnot else | 23:13 |
| freemangordon | it is in co-processor, no data in TRM | 23:14 |
| freemangordon | whatever co-processor c15 means | 23:14 |
| DocScrutinizer | you might want to talk to jacekowski in #maemo, he also knows a bit about that early boot and coproz et al stuff | 23:18 |
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| DocScrutinizer | as long as we can't find an official word about what that reg does or looks like on boot, and we don't know bootrom/xloader touching it, and we have indications the thumb is flawed by a SiERR related to it, we can't consider thumb safe by any metrics | 23:20 |
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| freemangordon | agree | 23:20 |
| freemangordon | I will try to workaround first errata without enabling IBE bit | 23:21 |
| DocScrutinizer | unless of course we could show the situation that triggers this particular SiERR can never happen on N900 under fremantle | 23:21 |
| freemangordon | well, it seems to be the case, but lets wait till the end of a week | 23:22 |
| DocScrutinizer | we'd then live with an open barrel of gunpowder but nobody ever enters the room with any light or cigarette | 23:22 |
| freemangordon | as my /var/lib/dsme/stats is still empty | 23:23 |
| DocScrutinizer | and it's not enough state "this place isn't that croded, how likely is it somebody cmes by with a burning cigarette" - no we have to make *sure* nobody ever does. I.E. publish a howto advisory what code sequence never must get used, etc | 23:24 |
| DocScrutinizer | there might be assembler hackers out there that code shit your gcc never would produce | 23:24 |
| freemangordon | well, there is fix in binutils for another errata | 23:25 |
| DocScrutinizer | from the cursory read of MLs I think indications were they "tested" it with heavy load, means: many context switches | 23:26 |
| freemangordon | and I assume it working, as same (or similar) fixes exists in another arm compilers/linkers | 23:26 |
| freemangordon | paid ones | 23:26 |
| DocScrutinizer | sure, still that fix might work just golden in thumb-only environment | 23:27 |
| freemangordon | AIUI, it artificially swithes to arm and then again to thumb, or something like that. Should always work | 23:28 |
| DocScrutinizer | an OS with mixed-mode operation may still behave quite different to a WRT router compiled ALL for thumb | 23:28 |
| DocScrutinizer | on an all-thumb system there can't be arbitrary switches between thumb and arm mode | 23:29 |
| freemangordon | well, we know wor sure gcc version in scratchbox produses buggy code from time to time, so what, shall we stop using it? | 23:29 |
| freemangordon | for plain arm | 23:29 |
| DocScrutinizer | o.O | 23:29 |
| freemangordon | yes, remember Qt raster engine? | 23:30 |
| DocScrutinizer | bbl | 23:30 |
| freemangordon | ok | 23:30 |
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