IRC log of #maemo-ssu for Friday, 2016-04-15

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freemangordonsailus: " 40:        599      INTC  24 Edge      480bd400.mmu, OMAP3 ISP" :)20:30
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freemangordonPali: ^^^ we got ISP interrupts, still no image, but at least there are signs of life20:49
Palinice!!!!20:50
freemangordonPali: to achieve that, I remove video-bus-switch20:50
freemangordon*removed20:50
freemangordonwe should contact sre20:51
Paliyes20:51
freemangordonbut first, I will try to have something but green image displayed20:52
DocScrutinizer05make sure your video bus switch (actually mux) doesn't operate inverted, enabling front cam when you want main and vice versa21:07
DocScrutinizer05check GPIO_9721:09
freemangordonDocScrutinizer05: no way, i2c bus is switched there as well21:09
freemangordonyes, I do that switching by hand21:09
DocScrutinizer05duh! never noticed21:09
freemangordonhmm, wait21:09
freemangordonit is not i2c bus, my bad21:10
freemangordonbut gpio is connected to secondary camera reset21:10
freemangordonso if it is not the correct value, secondary camera is held in reset and does not respond to i2c bus red/writes21:10
freemangordon*reads21:10
DocScrutinizer05o.O21:11
freemangordonsee schemati, on page 221:11
DocScrutinizer05indeed, CAM_B_EN21:11
freemangordonyeah21:11
DocScrutinizer05is this actually reset on front cam module?21:12
freemangordonhmm, I get lots of error IRQs21:12
freemangordonno, it has another gpio for reset (102)21:12
DocScrutinizer05error IRQ?21:12
freemangordonyes21:12
DocScrutinizer05please elaborate21:13
freemangordonsee CSI1B_IRQSTATUS in TRM21:13
freemangordonI get 0x615 here :D21:13
DocScrutinizer05aah ok21:13
DocScrutinizer05you got a pagenumber of TRM for me?21:14
freemangordonsure21:14
freemangordon153821:14
freemangordonTable 12-138.21:14
DocScrutinizer05SPRS599D  ?21:15
freemangordonOMAP34xx_ES3.1.x_PUBLIC_TRM_vZM.pdf21:15
DocScrutinizer05so SPRUF98?21:18
freemangordonDocScrutinizer05: http://46.249.74.23/TRM/21:19
DocScrutinizer05ohmy21:19
freemangordonDocScrutinizer05: SWPU223M21:20
DocScrutinizer05thanks! :-)21:24
DocScrutinizer05"bit NNN value 0x0" ??? 0x ?21:26
freemangordonhmm?21:26
freemangordonDocScrutinizer05: elaborate, please21:27
DocScrutinizer05a bit weird to give a hex value for a one bit var21:27
freemangordonone bit?21:27
freemangordonDocScrutinizer05: CSI1B_IRQSTATUS21:27
DocScrutinizer05http://wstaw.org/m/2016/04/15/plasma-desktopug2219.png21:28
freemangordonaah21:28
freemangordonwell21:28
DocScrutinizer05minor but puzzling21:28
freemangordonactually not, as this is *field* value21:29
DocScrutinizer05you got 0x615?21:29
freemangordonit might be longer than 1 bit21:29
DocScrutinizer05yes21:29
freemangordonthe first is e11, then 411, then 615, which repeats countless times21:30
freemangordon615 is the one that repeats21:30
DocScrutinizer050b1100001010121:30
freemangordonso, yeah21:30
freemangordon11100001000121:31
freemangordone1121:31
freemangordonthat bit 4 (reserved) is actually CRC error21:32
freemangordonaccording to the kernel code21:32
DocScrutinizer05mhm21:32
freemangordonhmm, KP explicitly sets crc to 021:33
DocScrutinizer05according to TRM you write 1(!) to it to reset21:34
DocScrutinizer05sounds weird21:34
freemangordonso?21:34
DocScrutinizer050x0: READS: Event is false. WRITES: Status bit unchanged.        0x1: READS: Event is true (pending). WRITES: Status bit is reset.21:35
DocScrutinizer05actually e11 doesn't look like too much of an error, most are just sync notifications21:36
DocScrutinizer05just that CRC bit 421:36
DocScrutinizer05aiui21:36
DocScrutinizer05and SSC_IRQ bit 021:37
DocScrutinizer05which means it's not synced yet21:37
DocScrutinizer05again aiui21:37
freemangordonok, CRC disabled, bit 4 is down21:38
freemangordonstill no image21:38
freemangordonDocScrutinizer05: those sync errors mean that no image will appear21:38
DocScrutinizer05I seem to recall you need to write a sync byte (word?)  to cam sensor's "upper left pixel"21:39
freemangordonDocScrutinizer05: never heard of that21:39
DocScrutinizer05cloudy memories21:40
DocScrutinizer05maybe it's hardwired in sensor21:40
DocScrutinizer05hmm, sort of there it is: >> Each frame is clearly identified by four unique 32-bit synchronization codes: frame start, frame end, line start, and line end, which are embedded in the serial bitstream. The logical channel identification number is also encoded in the synchronization codes.<<  p132421:47
DocScrutinizer05table 12-8 Sync codes21:48
freemangordonDocScrutinizer05: those codes are the same in stock kernel21:49
freemangordonalready checked21:49
DocScrutinizer05:nod:21:49
freemangordon321021:49
DocScrutinizer05sorry, afk. Prolly I'm not much of a help anyway21:49
DocScrutinizer05Figure 12-57. CSI1 Receiver Block Diagram    - first thing after CSI input is "Extract SYNC"21:53
freemangordonyep, but this is CSI1 that gives errors21:53
freemangordonso nothing gets out21:53
DocScrutinizer05yes, it seems it doesn't sync21:54
DocScrutinizer05on a very low layer21:55
freemangordon:nod:21:55
DocScrutinizer05bbl21:55
freemangordonhowever, this is still HUGE success, so far we've never got ISP interrupts21:55
freemangordon*get21:55
DocScrutinizer05check module config21:57
DocScrutinizer05(huge success) :-)21:57
DocScrutinizer05wait, I got some bookmark to some useful contribution regarding camera, from a dunno Jolla devel or sth?21:58
DocScrutinizer05I'll try to find that later21:58
freemangordonok21:59
DocScrutinizer05aah21:59
DocScrutinizer05~fptf21:59
infobotextra, extra, read all about it, fptf is the Fremantle Porting Task Force, see http://talk.maemo.org/showthread.php?t=9130821:59
DocScrutinizer05About camera (about meego/sailfish, but for stuff like zerocopy and omap3camd and how stuff works it applies to fremantle as well, more or less): http://talk.maemo.org/showthread.php...55#post139715522:00
DocScrutinizer05hmm, prolly irrelevant here, not kernel related22:01
DocScrutinizer05or is it? omap3camd?22:01
DocScrutinizer05anyway, afk for good now22:04
freemangordonYEEEAAH22:04
freemangordongot frames in mplayer!!!22:05
freemangordonPali: ^^^ :)22:06
Sicelo\m/22:06
Paliwau!!22:06
freemangordonwell, there still no video, but no green only as well, I guess I need to tweak brightness etc22:11
freemangordonwaw, test patterns seem to work :)22:13
freemangordon*wow22:13
Sicelowhat test patterns? :)22:18
freemangordonvertical strips22:20
freemangordoncolor bars22:20
freemangordon 0: Disabled22:20
freemangordon  1: Solid Colour22:20
freemangordon  2: Eight Vertical Colour Bars22:20
freemangordon  3: Colour Bars With Fade to Grey22:20
freemangordon  4: Pseudorandom Sequence (PN9)22:20
DocScrutinizer05:-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/22:21
DocScrutinizer05amazing what a lil bit of syncing can do, eh? ;-)22:22
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freemangordonwell, those bars are heavily distorted, I see way more than 8, an they are almost horizontal22:22
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DocScrutinizer05wait, who generates the test patterns? cam module or CSI interface in SoC?22:22
freemangordonbut this ia a matter of tweaking22:22
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freemangordonI guess it is cam module22:23
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DocScrutinizer05(distorted) sounds like wrong resolution22:24
freemangordonrather wrong pixel rate22:24
DocScrutinizer05aka dividers for DMA addressing22:24
freemangordonwell, there are at least 10 dividers :D22:24
DocScrutinizer05pixel rate is sort of fixed, err synced. CSI has a clock and data differential line22:25
freemangordonno, it is not22:25
freemangordoncamera module gets external clock and has its own pll22:25
DocScrutinizer05it's not fixed, it's controlled by cam module aiui, and the CSI IF is synced to that22:25
DocScrutinizer05aah ok22:25
DocScrutinizer05then the cam PLL can be off too22:26
freemangordonloks like, as it reports `Pixel Rate' min 0 max 0 step 0 default 0 current 12000000.22:26
freemangordonhmm, this might be ok22:27
DocScrutinizer05anyway you got (at least) one modulo divider for horizontal and one for vertical addressing in DMA on SOC, and you get a resolution setting that prolly works similar in cam module, both must match or the wrong pixel data will end on the wrong RAM address22:28
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freemangordonthe pipeline is way more complicated, you have CSI then CCDC then previewer then resizer :)22:29
DocScrutinizer05sync between the two modulo divider groups gets done by CSI clk and table 12-8 Sync codes22:29
DocScrutinizer05yeah sure there is more complicated stuff in it than just taht22:30
DocScrutinizer05particularly resizing is 'fun' to get right, I guess22:30
freemangordonanyway, I think I did enough for today, will wait for sailus to appear to give some hints on where to look at22:31
DocScrutinizer05good job, you earned your glass of spirit of your choice ;-D22:36
freemangordon:)22:36
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