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| merlin1991 | Sicelo: I'll have a look at that | 14:49 |
|---|---|---|
| merlin1991 | Sicelo: I can't reproduce it on testing or stable | 14:54 |
| merlin1991 | MohammadAG: new testing this weekend? :) | 14:55 |
| freemangordon | merlin1991 could you please pull git@gitorious.org:fremantle-720p-support/osso-camera-ui-l10n.git in CSUU repo | 14:58 |
| freemangordon | *CSSU | 14:58 |
| Pali | merlin1991, can you also push into CSSU patched osso-calculator-engine? | 15:06 |
| freemangordon | Pali, any plans to move KP in CSSU? | 15:08 |
| Pali | what? | 15:08 |
| Pali | why? | 15:09 |
| freemangordon | Because omap1 is dated | 15:10 |
| freemangordon | well, not exactly KP, but KP with stripped capabilities | 15:11 |
| freemangordon | overclocking stuff and such | 15:11 |
| Pali | so only bugfix to CSSU? | 15:11 |
| freemangordon | well, new functionality too, new modules, etc. | 15:11 |
| freemangordon | those that don't have known issues | 15:12 |
| Pali | ok, but ask merlin1991 and MohammadAG | 15:12 |
| freemangordon | see, I am not talking about moving KP in CSSU today. For the fiture. | 15:12 |
| freemangordon | *future | 15:13 |
| freemangordon | of course I will :D | 15:13 |
| freemangordon | actually it should be done in some meeting | 15:13 |
| Pali | there will be problem with upgrading via HAM | 15:13 |
| Pali | users with KP will get update too | 15:13 |
| merlin1991 | and users with other kernel too | 15:13 |
| freemangordon | see, after all thumb seems rock stable, new DSP driver is in KP, all that stuff | 15:14 |
| freemangordon | both? | 15:14 |
| freemangordon | sorry, misread, scratch that | 15:14 |
| freemangordon | Pali, what if users of KP get the update? | 15:14 |
| Pali | if they get CSSU kernel update, it will flash and replace cssu kernel | 15:15 |
| freemangordon | well, that is some maintaner work to do, what if they flash newer KP over CSSU one? | 15:16 |
| freemangordon | it is the same now | 15:16 |
| freemangordon | but you have omap1 instead of cssu1 | 15:16 |
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| freemangordon | bbl | 15:17 |
| MohammadAG | I already suggested we check in postinst if a different kernel flavor exists | 15:24 |
| MohammadAG | if so prompt the user on what to do | 15:25 |
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| fw190 | hello | 18:11 |
| fw190 | any news about uboot for kp49 or later? | 18:11 |
| merlin1991 | fw190: it's only a matter of doing it | 18:14 |
| merlin1991 | I had the requirements in place at some point, but don't have it anymore | 18:15 |
| fw190 | hmmm would be greatfull- it's needed for testing nemombile. can't leave kp for it so im in fead end ;) | 18:18 |
| fw190 | dead | 18:19 |
| merlin1991 | though that question wasn't exactly cssu related :D | 18:21 |
| fw190 | it isn't but dont know where to ask... | 18:21 |
| merlin1991 | #maemo? :D | 18:22 |
| fw190 | ok you got me ;) | 18:23 |
| fw190 | so now for something cssu related | 18:23 |
| fw190 | maybe we could change te meeting schedule? | 18:23 |
| merlin1991 | to what? | 18:24 |
| fw190 | maybe this could be a daily chit chat if something interesting would pop uout? | 18:24 |
| merlin1991 | we do have a 24/7 chit chat since this is irc :D | 18:24 |
| merlin1991 | the meeting schedule was meant for people who don't end up on irc usually | 18:25 |
| fw190 | ah now I understand | 18:26 |
| fw190 | but decisions are made on the meetings | 18:26 |
| fw190 | but sometimes we are missing some key members and there are no meetings or no decisions can be made | 18:26 |
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| freemangordon | DocScrutinizer, ping | 21:11 |
| DocScrutinizer51 | pong | 21:12 |
| freemangordon | PM-ed something, worth reading | 21:12 |
| DocScrutinizer51 | pm as in? | 21:12 |
| freemangordon | personal messgage | 21:13 |
| freemangordon | message* | 21:13 |
| freemangordon | on TMO | 21:13 |
| DocScrutinizer51 | to? | 21:13 |
| DocScrutinizer51 | aah | 21:13 |
| freemangordon | joerg_rw | 21:13 |
| DocScrutinizer51 | omg | 21:13 |
| freemangordon | ? | 21:13 |
| * DocScrutinizer51 hates this friggin tmo pm | 21:13 | |
| freemangordon | yep, but there is a reason. | 21:14 |
| DocScrutinizer51 | hmm | 21:14 |
| DocScrutinizer51 | couldn't figure any | 21:14 |
| DocScrutinizer51 | I'll see when I eventually come across it | 21:14 |
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| DocScrutinizer | freemangordon: I tend to support your notion, slowly but a bit more every day | 21:29 |
| freemangordon | :D good | 21:31 |
| DocScrutinizer | still reluctant to dive into all thumb head-first, without decent benchmarks. Also a proper forced context switching benchmark and stresstest would tell us a lot more than random tests on a whole system. But... yes, your argumentation is straight and sound | 21:31 |
| freemangordon | DocScrutinizer, BTB flush workaround is enabled in KP for an year or so, too late for benchmarks. | 21:33 |
| freemangordon | bbl | 21:33 |
| DocScrutinizer | we got no thumb binaries - basically - though | 21:33 |
| freemangordon | it affects all binaries, not only thumb. It invalidates BTB on every context switch no matter if code is thumb or not | 21:34 |
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| DocScrutinizer | 1) I need to read and understand that SiERR and what this BTB thing actually does. 2) I need to know if it'S a thumb-only thing or has impact on system performance in all situations. 3) we still need some *real* numbers so we can do an educated guess rather than stating "nobody complained so far" as that'S actually not correct: users complain all the time about a zillion of things, and we don't even know exactly what particular side | 21:36 |
| DocScrutinizer | effects flushing BTB might show on our fremantle system | 21:36 |
| DocScrutinizer | well, you answered a few of my points as I needed so long to type | 21:37 |
| DocScrutinizer | :-D still we need better stories about all this | 21:37 |
| DocScrutinizer | maybe the scheduler flushes BTB on every context switch, but is arm code actually using BTB? - for example | 21:38 |
| DocScrutinizer | I need to see a in-depth theoretical evaluation of the impacts this btb-flush fix has, under some selected situations | 21:39 |
| DocScrutinizer | to specify what exactly I need to see, I first have to understand what the fix does, which in turn needs me to understand what btb does | 21:40 |
| DocScrutinizer | and how it's been handled in context switches before that patch, how it's handled now with this patch, and how all this fits into the SiERR thing | 21:41 |
| DocScrutinizer | then when we've done all this correctly, we can publish an official "this bug got fixed" announcement that is applicable to all similar hw | 21:42 |
| DocScrutinizer | not only to N900 | 21:42 |
| DocScrutinizer | actually you'll do that, and you're free to mention my help when doing so. Then we basically "import the bugfix" from upstream | 21:43 |
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| freemangordon | DocScrutinizer, BTB is a kind of cache memory used by branch predictor, i.e. when a predicted (or not) branch is taken the logic searches BTB if VA address of the branch target is there, if it is there, the branch is taken using PA(physical address) from BTB. The effect is that we skip VA->PA translation which has very good performance impact. But I would trade even 10% of performance for | 22:01 |
| freemangordon | 40MB of free RAM on n900 | 22:01 |
| freemangordon | 40MB *MORE* free ram | 22:02 |
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| DocScrutinizer | I bet it's no 10% we will have to suffer from, for the mere BTB flush. But we need a proper analysis if the one SiERR is evidently fixed by this. And we need a rough estimation about the actual impact on performance, in percent_increased_contextswitching_time plus a rough picture how many context switches usually and under worst case can happen per time. | 22:40 |
| DocScrutinizer | ooh, of course plus impact on code execution *after* context switch. Along the line "BTB depth: 16 branches. Time to fill one BTB position vs time to execute a branch based on a valid BTB position: NN clock cycles. Ergo: 16*NN = max penalty for each taskswitching. Plus penalty for the flushing during taskswitching: NN cycles. Estimated avrg taskswitches / second: 50. Total avrg penalty: clockcycles/s / (50 * sigma(penalties per switch))" | 22:47 |
| freemangordon | And how we are going to evaluate penalty for BTB flush against speed gain because of more free RAM, better cache usage (because of the shorter code), less swapping, etc. Not sure it is possible to do such evaluation. | 22:52 |
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| DocScrutinizer | all is possible | 22:56 |
| freemangordon | hmm, trust me on that(tm) approach seems more feasible to me than some indepth academical research, I am not going to do it. | 22:57 |
| DocScrutinizer | we however are not even really interested in that, as that's our private pet thing, not sth about fixing a SiERR properly. In the end it's up to the end user to decide if she prefers more free RAM or faster code, all we can and have to do is deliver proper fix and evaluation of the impact it brings | 22:57 |
| freemangordon | you mean non-n900 users? | 22:58 |
| DocScrutinizer | and more important than impact analysis is evaluation of general validity of the fix, performance impact estimation comes "for free" with that | 22:59 |
| DocScrutinizer | actually that'S sth the original author of the fix should have done, I'm wondering why he didn't | 23:01 |
| freemangordon | I think I have done enough analysis these days, just need to gather all the pieces. And send a mail to maemo-developers or such. | 23:01 |
| freemangordon | it is done | 23:01 |
| freemangordon | by the original author | 23:02 |
| DocScrutinizer | so why don't you just share a URL so we all could read it up by ourselves? :-) | 23:02 |
| DocScrutinizer | will save us lots of analysis and evaluation work | 23:03 |
| freemangordon | +bool "ARM errata: Stale prediction on replaced interworking branch" | 23:03 |
| freemangordon | +depends on CPU_V7 | 23:03 |
| freemangordon | +help | 23:03 |
| freemangordon | + This option enables the workaround for the 430973 Cortex-A8 | 23:03 |
| freemangordon | + (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb | 23:03 |
| freemangordon | + interworking branch is replaced with another code sequence at the | 23:03 |
| freemangordon | + same virtual address, whether due to self-modifying code or virtual | 23:03 |
| freemangordon | + to physical address re-mapping, Cortex-A8 does not recover from the | 23:03 |
| freemangordon | + stale interworking branch prediction. This results in Cortex-A8 | 23:03 |
| freemangordon | + executing the new code sequence in the incorrect ARM or Thumb state. | 23:03 |
| freemangordon | + The workaround enables the BTB/BTAC operations by setting ACTLR.IBE | 23:03 |
| freemangordon | + and also flushes the branch target cache at every context switch. | 23:03 |
| freemangordon | + Note that setting specific bits in the ACTLR register may not be | 23:03 |
| freemangordon | + available in non-secure mode. | 23:03 |
| RST38h | please stop | 23:03 |
| freemangordon | sorry | 23:04 |
| RST38h | pastebin | 23:04 |
| freemangordon | http://pastebin.com/FLCVKqfb | 23:05 |
| freemangordon | DocScrutinizer ^^^ | 23:06 |
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